1. Field
Exemplary embodiments of the present invention relate to semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit including a filtering circuit.
2. Description of the Related Art
In general, a semiconductor memory device such as double data rate synchronous DRAM (DDR SDRAM) includes a delay locked loop (DLL) that is configured to compensate for time delay caused by an internal circuit such that an internal clock signal and an external clock signal have the same phase, when the external clock signal inputted from a circuit outside of the semiconductor memory device is used inside the semiconductor memory device. In other words, the DLL receives the external clock signal and compensates for a delay component in an actual clock path and data path to previously reflect negative delay. Accordingly, data outputted from the semiconductor memory device may be synchronized with the external clock signal.
FIG. 1 is a block diagram of a conventional DLL.
Referring to FIG. 1, the DLL 100 includes an input buffer unit 110, a variable delay line 120, a replica delay 130, a phase comparator 140, a filtering unit 150, a delay control unit 160, an output driver 170, and a data output unit 180. The input buffer unit 110 is configured to buffer an external clock signal EXTCLK and output an internal clock signal INTCLK. The variable delay line 120 is configured to delay the internal clock signal INTCLK by a delay time required for locking in response to a delay control signal DELYCTL, and output a delay locked clock signal DLLCLK. The replica delay 130 is configured to delay the delay locked clock signal DLLCLK by a delay time occurring in an actual clock path and data path and output a feedback clock signal FBCLK. The phase comparator 140 is configured to compare the phase of the internal clock signal INTCLK with of the phase of the feedback clock signal FBCLK. The filtering unit 150 is configured to generate filtered comparison signals INC and DEC in response to a comparison signal PDOUT outputted from the phase comparator 140 and a control clock signal CTRLCLK. The delay control unit 160 is configured to generate a delay control signal DELYCTRL in response to the filtered comparison signals INC and DEC. The output driver 170 is configured to drive the delay locked clock signal DLLCLK. The data output unit 180 is configured to output data signals RDATA and FDATA to a data pad DQ in synchronization with a delay locked clock signal DLLCLK′ driven by the output driver 170.
FIG. 2 is an internal configuration diagram of the filtering unit 150 illustrated in FIG. 1.
Referring to FIG. 2, the filtering unit 150 includes a sampling unit 152 and output sections 154A and 154B. The sampling unit 152 is configured to sample the comparison signal PDOUT in synchronization with the control clock signal CTLCLK, and the output sections 154A and 154B are configured to output filtered first and second comparison signals INC and DEC in response to output signals A to E of the sampling unit 152.
The sampling unit 152 successively shifts the comparison signal PDOUT by a designated sampling number (for example, five) and outputs successively-shifted comparison signals A to E. The sampling unit 152 may include D flip-flop chains DFF0 to DFF4.
Furthermore, the output sections 154A and 154B include a first output unit 154A configured to perform an AND operation on the shifted comparison signals A to E and output a filtered first comparison signal INC, and a second output unit 154B configured to perform a NOR operation on the shifted comparison signals A to E and output a filtered second comparison signal DEC. For example, the first output unit 154A may include an NAND gate NAND configured to perform an NAND operation on the shifted comparison signals A to E and an inverter INV configured to invert an output signal of the NAND gate NAND, and the second output unit 154B may include a NOR gate NOR configured to perform a NOR operation on the shifted comparison signals A to E.
Hereafter, the operation of the DLL 100 configured in such a manner will be described.
During initial driving, when an external clock signal EXTCLK is buffered by the input buffer unit 110 and transmitted as an internal clock signal INTCLK to the variable delay line 120, the variable delay line 120 bypasses the internal clock signal INTCLK.
The replica delay 130 receives a delay locked clock signal DLLCLK outputted from the variable delay line 120, delays the received signal by a modeled delay time, and outputs a feedback clock signal FBCLK to the phase comparator 140.
The phase comparator 140 compares the phase of the internal clock signal INTCLK outputted from the input buffer unit 110 with the phase of the feedback clock signal FBCLK outputted from the replica delay 130 and transmits a comparison signal PDOUT corresponding to the comparison result to the filtering unit 150.
The filtering unit 150 filters the comparison signal PDOUT and outputs filtered comparison signals INC and DEC. In the filtering unit 150, the filtering is performed to determine whether the comparison signal PDOUT is a jitter or not. During the filtering, the comparison signal PDOUT is sampled by a designated sampling number (for example, five) to determine whether the comparison signal PDOUT is a jitter or not. FIG. 3 shows the filtering operation. Referring to FIG. 3, when all of the signals A to E obtained by successively shifting the comparison signal PDOUT have a logic high level, the filtered first comparison signal INC is activated to a logic high level. In other words, when the sampling results A to E obtained by sampling the comparison signal PDOUT five times have the same value, the comparison signal PDOUT is determined to be a normal comparison signal, and the filtered first or second comparison signal INC and DEC is activated. On the other hand, when any one of the sampling results A to B has a different value, the comparison signal PDOUT is determined to an abnormal comparison signal, more specifically, a jitter, and the filtered first and second comparison signal INC and DEC are not activated. As a result, the filtering unit 150 activates the filtered first or second comparison signal INC and DEC only when the comparison signal PDOUT continuously has a constant logic level during five periods (5tCK) of the control clock signal CTRCLK.
The delay control unit 160 generates a delay control signal DELYCTRL according to the filtered first and second comparison signals INC and DEC outputted from the filtering unit 150, and outputs the generated signal to the variable delay line 120. Here, when the filtered first comparison signal INC is activated, the delay control unit 160 outputs a delay control signal DELYCTRL for increasing the delay time of the variable delay line 120. On the other hand, when the filtered second comparison signal DEC is activated, the delay control unit 160 outputs a delay control signal DELYCTRL for decreasing the delay time of the variable delay line 120.
The variable delay line 120 delays the internal clock signal INTCLK by a designated delay time in response to the delay control signal DELYCTRL, and outputs the delay locked clock signal DLLCLK.
When the above-described series of operations are repeated and the phases of the internal clock signal INTCLK and the feedback clock signal FBCLK are synchronized according to the comparison result of the phase comparator 140, the delay time of the variable delay line 120 is delay locked.
Meanwhile, after the delay time required for locking the variable delay line 120 is decided, an update process is performed every designated period. The update process is repetitively performs the above-described locking process to adaptively deal with an environment change. The locking process is referred to as a tracking process. When the update process is performed, a jitter may occur. In this case, since the jitter is filtered, the update process is not incorrectly performed. When the update process is performed by a jitter, a jitter caused by the update process is added to the occurring jitter, and thus a jitter of the final output further increases. For reference, the above-described jitter includes a voltage jitter and a clock jitter. The voltage jitter component may be caused by a defect of an external power supply device, a coupling of voltage transmission lines, and a voltage drop by an internal operation of the DRAM (not illustrated) including the DLL 100, and the clock jitter may be caused by a defect of an external clock supply device and a coupling of clock transmission lines.
According to the above-described DLL 100, the wrong update process by the jitter is not performed.
However, the DLL 100 may have the following features.
As described above, the filtering unit 150 performs a function of filtering the comparison signal PDOUT outputted from the phase comparator 140. More specifically, when the comparison signal PDOUT is activated, the filtering unit 150 determines whether the comparison signal PDOUT is a normal comparison signal for tracking or an abnormal comparison signal caused by a jitter. As a determination result, when the comparison signal PDOUT is an abnormal comparison signal, the filtering unit 150 ignores the comparison signal PDOUT, and when the comparison signal PDOUT is a normal comparison signal, the filtering unit 150 activates the filtered comparison signals INC and DEC. At this time, the determination method may include a process of sampling the comparison signal PDOUT by a designated sampling number (for example, five). For example, sampling may include whether the activation unit of the comparison signal PDOUT is maintained during five periods (5tCK) of the control clock signal CTRLCLK or not. However, since the sampling number is fixed when the filtering unit 150 performs a filtering operation, a situation handling ability may decrease. When the sampling number is increased to improve the jitter determination ability, the tracking period (or update period) is lengthened, thereby increasing a time required for tracking the delay locked clock signal DLLCLK. On the other hand, when the sampling number is decreased to reduce the tracking period (or update period), the jitter determination ability decreases. For reference, when the tracking period (or update period) is lengthened, a quick tracking operation is not performed where a situation such as ‘voltage bump’ occurs, and thus a malfunction becomes severe. The voltage bump may include when an unintended voltage drop occurs or when a voltage drop is intentionally caused for power reduction.
Therefore, a sampling number should be suitable for all situations. However, since an optimal sampling number differs depending on situations, a common optimal sampling number may be difficult to decide.